Command reference

General syntax

Commands are specified by the following general syntax:

The command string exists of ASCII characters. The command parameters (param) may be one of the following types:

Commands should be terminated or seperated with a CR (13 dec or 0xD), LF (10 dec or 0xA) or semicolon (;). The ATX7002 will end a respond with a CR.

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AF | Analog full scale of device

The Device under test (ADC or DAC) Full Scale value specifies the voltage level corresponding to the expected full scale level (often equal to Vref). The parameter is used to calculate the expected output value (analog or digital) of the DUT, after a conversion, for the error calculations.

Related commands: AZ, AG, AO, AI, GO.

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AG | Analog gain

After the DUT parameter definition, like full-scale voltage (AF), zero scale voltage (AZ) number of device bits (DB), it is possible to calculate the ideal conversion result because for each conversion result, the corresponding ATX DAC output voltage is known. However, when on the test board, an input amplifier or a filter is situated, the expected code on the output is unknown due to signal gain or attenuation. With the Analog Gain command, the user can define the attenuation or gain of the signal-path between the ATX DAC output and the device input.

Related commands: AO, AI, GO.

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AI | Analog Input offset voltage

This command defines the actual device input offset voltage or ATX ADC input offset. This parameter is only used if parameter GO is set to 0. For A/D measurements, it is possible that a DC component programmed in the voltage from the ATX DAC is blocked out of the DUT input signal, due to filtering. In this case, it is possible that an offset voltage is applied to the device input by an external reference source or by the input amplifier stage. This voltage should be known to calculate the expected output codes of the DUT.

Related commands: AG.

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AN | Analog ramp minimum

When using the Ramp measurement, AN configures the starting voltage of the A/D ramp . The negative reference voltage of ATX output DAC is programmed to this voltage, meaning that the lower limit of the ATX DAC voltage is set by this command.

Related commands: AX.

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AO | Analog offset for sine waves

The offset voltage [volts] defined with this command, is added to all defined sine waves. The offset is not used during ramp-measurements.

Related commands: AS.

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AS | Analog sine

This command defines the stimulus signal parameters for harmonic A/D converter tests. It is possible to define up to 10 different sine waves. Definition should start with sine 0. All sine waves are added and stored in the stimulus memory. The sine waves can be defined by giving the amplitude (top), and the number of periods within the defined stimuli size (SS). An offset (used for all sines) can be defined with the AO command. De frequency of the sine wave is depending on the number of periods defined here, the number of stimuli steps and the stimulus clock period time. This sample clock can be either f = periods/( SS x t(clock) ) , an external (user) clock or a clock generated by the pattern bits (BHSO) or BHSI, see the CS command for details.

The number of periods should be an integer higher or equal to one, the phase is a float variable, defining the sine wave phase in degrees.

NOTE: After defining the sine waves, the stimulus memory size, the stimulus memory should be updated with the "Stimuli Fill" command (SF). The ATX DAC ranging is automatically set to the minimum and maximum signal level, in the stimulus signal.

For generating signals with an AWG module and high signal frequencies relative to the samplefrequency, please be aware of the sinc attenuation. An online sinc attenuation calculator can be found here.

Related commands: AO.

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AU | Analog utilization factor

Only applicable for MT2 (A/D dynamic test).

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AX | Analog ramp maximum

When using the Ramp measurement, AX configures the end voltage of the A/D ramp. In combination with the AN parameter, AX determines the output sweep and ATX DAC resolution. The atx DAC sweep can be easily calculated by subtracting AN from AX. The resolution of the 18 bit ATX DAC can calculate:

Related commands: AN.

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AZ | Analog zero scale

AZ specifies the voltage level corresponding to the zero scale level of the ADC or DAC under test (often equal to GND). The parameter is used for the calculation of the expected output value (analog or digital) of the DUT, after a conversion, for the error calculations.

Related commands: AF, AG, AO, AI, GO.

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C | Select Card

This command selects one of the Cards (modules). All other Card Setting commands operate on the selected Card only. It is also possible to select the card by typing the card number in front of these card setting commands. This makes the use of the C command needless.

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CBAUD | Baud rate

The Baud rate of the serial communication may be changed to one of the following values:
9600 19200 38400 57600* * Factory setting

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CC | Card Connect

In case of a signal DAC (AWG18) module, n selects the way the output signal is connected to the connector: In four wire mode (+Force +Sense, GND and GND sense), in two wire mode (The sense lines are internally connected to +force and GND) and in two wire 50 ohms mode (The output impedance of the module is 50 ohms). m selects the internal low pass filter setting :

*Always 50 Ohm connected

In case of an ADC module, n selects the input mode (Differential or single ended) and input impedance (50 ohms or 10 M ohms) of the ADC module.

In case of the high speed ADC module the n parameter is split in 2 digits n1 and n2. n1 (upper digit) for the positive input, n2 (lower digit) for the negative input.

If the card has two channels (in case of a reference DAC or power-DAC ) m determines the way the second channel is switched.

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CCLKD | High Speed DIO Clock Calibration data

These values are factory settings. Do not changes these values.

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CLKD | High Speed DIO Clock delay(s)

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CDIOV | Calibrate Digital Output levels

The last two parameters, minv and maxv, are optional. Code is a value between 00 and FF hexadecimal. With code 00 the digital output level is programmed to minimal voltage, with code FF to maximal voltage. If both voltages are measured, send this command with both voltage filled in to the ATX7002 (code may be any value).

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CGAIN | Calibrate Gain

Write gain value to selected module.

Signal DAC:

n is gain value of the offset dac. Gain should be calibrated at -5V and +5V.
m is gain value of the range dac. Gain should be calibrated at 0 and 10 V.

Signal ADC:

n is gain value of ADC.
Gain should be calibrated for each range.

Power DAC:

n is gain value of channel 1. Gain should be calibrated at -10V and +10V.
m is gain value of channel 2. Gain should also be calibrated at -10V and +10V.

Reference DAC:

n is gain value of channel 1. Gain should be calibrated at -5V and +5V.
m is gain value of channel 2. Gain should also be calibrated at -5V and +5V.

Store values in the module eeprom after calibration with the command CSTORE.

Related commands: COFFSET, CSTORE

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CID? | module identification

With CID, the module identification of the currently selected module can be read. This value should correspond with the CMOD command. See CMOD command for more information about module codes.

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CIEEE |IEEE address

IEEE address should be in a range from 0 to 30.

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COFFSET | Calibrate Offset

Write offset value to selected module.

Signal DAC:

n is offset value of the offset dac. Offset should be calibrated at 0V.
m is offset value of the range dac. Offset should be calibrated at 5 V.

Signal ADC:

n is offset value of ADC.
Offset should be calibrated for each range.

Power DAC:

n is offset value of channel 1. Offset should be calibrated at 0V.
m is offset value of channel 2. Offset should also be calibrated at 0V.

Reference DAC:

n is offset value of channel 1. Offset should be calibrated at 0V.
m is offset value of channel 2. Offset should also be calibrated at 0V.

Store values in the module eeprom after calibration with the command CSTORE.

Related commands: CGAIN, CSTORE

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CMOD | Module configuration

With CMOD, the module type of the currently selected module can be read. The following CMOD values are applicable:

• 01 DIO module
• 02 HSDIO/MFDIO
• 11 18 bit Signal DAC module
• 12 24 bit Signal DAC module
• 13 16 bit High Speed Dac module
• 21 18 bit ADC module
• 22 24 bit ADC module
• 23 14 bit ADC module
• 31 Dual power DAC module
• 41 Dual Reference DAC module
• 61 S2D+GA module

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CRC | Return CRC check

Related command(s): OM[B]

CS | module Clock Source

With this command the clock source of the ATX7002 DAC, ADC or DIO module can be selected. With CS set to 0, HSO is the clock source, with CS set to 1, HSI becomes the clock source. With CS2 the clock source of the DAC or ADC is set to an external user clock.
Example:

• CS1 set the module clock source to HSI.

CSTORE | Store calibration values

After calibrating a module (manually) with the commands COFFSET and CGAIN, this command stores the calibration values in an eeprom of the calibrated module. After power up the calibration values will be read from eeprom.

Related commands: CGAIN, COFFSET

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CV | set DAC voltage/read ADC voltage

Use this command to program the currently selected module output voltage. In case of a signal DAC, only one voltage can be programmed. This voltage should be between the current settings of AN and AX. In case of a dual reference DAC module or a power module, two voltages can be entered, ranging from -6.5V to +6.5V for a reference DAC and -13.5 to +13.5V for a dual powerDAC. The first voltage entered represents channel 1, the second voltage represents channel 2. In case of an ADC module, only the CV? command is valid. It returns the input voltage of the ADC.

Related commands: AN, AX, RA

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DB | number of Device Bits

This command specifies the bit-size (n=1..16) of the converter under test. The ATX firmware uses this information to determine step size, calculation of expected data and for error calculation purposes.

Related commands: AZ, AF

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DEM | Display Error Messages

With this command, it is possible to let the ATX send error messages back to the user, when an error occurred. To activate this function, DEM must be set to 1. The value 0 deactivates the function. Especially on testing and debugging command strings this can be helpful. After reset, the command is disabled.

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DIOM | DIO mode

Set the MFDIO module in the appropriate mode:

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DIOV | Digital Output levels

The voltage level of the digital output lines of the DIO module is adjustable between 1.8 and 3.3 V.

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DIV | clock divider

The sample clock of the 24 bit A/D or D/A module can be divided by a value between 1 and 255. The divided sample clock determines the sample frequency.

The divider for the MFDIO can have the values: 1,2,4,8.
The divider value for the AWG16-100 can have the values: 1,2,4,8,16,32,64,128,256.
The WFD1470 supports the sampledivider.

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DL | Device Latency

Due to pipelining, the device adds a certain latency, which is called the device latency. The user should define this device latency, so the firmware can find the capture data that corresponds with the stimulus data. For A/D measurement this value should be less than 16, for D/A measurements less than 14.

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DN | Digital ramp Minimum

The DN definition is used for calculation of a digital ramp, it defines the value of the first stimulus step. Since the stimulus memory is 20 bit, this value must be between 0 and FFFFF. After defining the digital ramp minimum, the stimulus memory should be updated with the SF command before the next measurement.

Related commands: DX

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DO | Digital sine Offset

The digital offset can be defined between 0 and FFFFFh, and is added to the digital sine stimulus signal. The result of this addition is stored in the stimulus memory and should be within the range 0..FFFFF. After defining the digital offset, the stimulus memory should be updated with the SF command before the next measurement.

Related commands: DS

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DS | Digital sine

This command defines the stimulus signal parameters for D/A converter dynamic tests. It is possible to define up to 10 different sinewaves. Definition should start with sine 0. With the Stimuli Fill (SF) command, all defined sinewaves are added and stored in the stimulus memory. The sinewaves can be defined by giving the hexadecimal ampitude(top), and the number of periods within the defined stimuli size (SS). A digital offset that is used for all sines should be defined with the DO command, to prevent the signal from "clipping". De frequency of the sinewave depends on the number of periods defined here, the number of stimulisteps and the stimulus clock period time. This sample clock can be either an external (user) clock or a clock generated by the patternbits (BHSO) or BHSI, see the CS command for details. The number of periods should be an integer higher or equal to one.

This sample clock can be either: f = periods/(SS x t(clock))

NOTE: After defining the sinewaves, and the stimulus memory size, the stimuli memory should be updated with the "Stimuli Fill" command (SF).

Related commands: DO, SS, SF

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DT | Device type

Dependent on the type of A/D converter, an offset correction must be taken in account for error calculation. For unipolar devices, the offset correction may be at 0 (DT=0) or 1/2 LSB (DT=1): DT0 With bipolar devices, the offset error and gain error are calculated with respect to halve scale (0V). A two’s complement bipolar device, should be measured with DT set to 3:

• DT0 : unipolar device, no offset correction : first transition is at 1 lsb from zero scale
• DT1 : unipolar device, the first transition is at 1/2 lsb from zero scale.
• DT2 : bipolar device, straight binary code.
• DT3 : Two’s complement.
• DT4 : Sigma delta modulator.

DT is a error calculation parameter. The measurement is not affected by this command.

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DX | Digital ramp Maximum

The DX definition is used for calculation of a digital ramp, it defines the value of the last stimulus step. Since the stimulus memory is 20 bit, this value must be between 0 and FFFFF. After defining the digital ramp maximum, the stimulus memory should be updated with the SF command before the next measurement.

Related commands: SS, DN, SF

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FS | fs-mode

For the 24 bit ADC module:

For the 24 bit DAC module:

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GA | gain and connection mode

Set the gain and connection mode of the Gain Amplifier path of the S2D+GA module.

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GO | Device Offset-Gain

GO is a parameter (0 or 1), defining the way in which the DC offset, supplied by the ATX signal DAC, is attenuated or amplified by the DUT-board. This way it is possible to define the actual offset voltage at the input-pin of the DUT, and can the expected conversion result be calculated in the right way. When GO=1, the device input offset is assumed to be amplified by or attenuated by the value defined by AG. If the offset on the device has no relation with the offset supplied by the ATX DAC, it is possible to define this offset with parameter AI.

Related commands: AO, AG, AI

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HM | Handshake mode

This command initiates active state of the handshake input lines (HSI1 and HSI2) and handshake output line (HSO). Note that the handshake lines are only used when the ATX7002 is in Handshake mode, set by the command IM. In pattern bit mode, The handshake lines are not used for handshaking.

Related commands: IM, IOHS

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ID? | Identification

The identification string exists of the equipment name, revision number and revision date.

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IM | I/O Mode

The I/O mode command specifies the handshake protocol used during A/D or D/A converter measurements. The ATX DIO can operate in two modes: a DSP-controlled handshake mode and a pattern bit mode, where a programmable pattern generator controls the complete timing of the measurement. This pattern generator has 16 individual programmable bits, eight bits are used for internal measurement timing and the remaining eight are available on the DIO connector for user-defined purposes. For programming the pattern generator, please refer to the description of the PBx commands.

In handshake and pattern bit mode, the converter data can transfer either parallel or serial. The I/O mode command also specifies this parallel or serial data transfer. The following settings for IM are applicable:

IM0: Parallel data transfer, HSO only

During A/D converter test, after each settling time, the digital input is examined, then the next step is performed. There is no handshaking, but HSO pulses, dependent on the setting of HM, positive or negative after each settling time. The falling edge of HSO updates the output of the ATX signal DAC module. The settling time should be long enough for the DAC module to stabilize and the DUT to convert. Since the digital IO lines are read asynchronously, the read can coincidence with a change of the converter output code. (Read during signal transition). The ATX7002 protects reading nonsense in these cases, by reading the data input with intervals of 300ns. If two consecutive data reads are similar, data is stored.

During D/A converter test, data changes on the DIO output. After the settling time, HSO goes active to indicate a sample is being taken: the ADC is sampled internally. To be sure of a valid output voltage, the DUT should perform at least two conversions within the defined sampling time.

IM1: Parallel data transfer, handshake mode (HSO and HSI)

During A/D converter test, after each settling time (TS), HSO goes active, (HSO active state is programmed with HM) to indicate that the A/D converter can start the conversion. The ATX first checks the status of HSI and, if necessary, waits until the HSI state is inactive. After HSO, the inactive state of HSI should be at least 4 us. The ATX now waits for the rising or falling edge of HSI1 (again programmed with HM). The active state of HSI should last for at least 2.5us. The latched input data is then read from the DIO input latches. After that, HSO is set inactive and the signal Dac is updated with the next voltage.

During D/A converter test, HSO indicates that the DIO output data is valid. The Dut then starts the conversion, and indicates on HSI 1 that its output voltage can be sampled. On HSI1, HSO returns to the inactive state. During AD and DA measurements, The ATX samples after a programmed timeout time, if for whatever reason HSI1 is not changed. This timeout time is defined with command TO.

IM2: Byte wise data transfer, handshake mode (HSO and HSI)

This I/O mode is implemented for a byte-wise digital input and is only for A/D converter type of measurements. For D/A measurements byte wise I/O is only supported in pattern bit mode (IM11). The handshaking is basically the same as described for IM1. The device data is divided in an least significant byte and a highest significant byte, and so the read is performed in two steps. HSI2 indicates the first byte read. HSI1 indicates the second byte read, and stores the total result in the capture memory. In IM2, the first read reads lowest significant byte.

IM3: Byte wise data transfer, handshake mode (HSO and HSI)

A Byte-wise I/O as described for IM2. Now the first read, on HSI2, reads the most significant byte.

IM10: Parallel data transfer, Pattern bit generated timing

The pattern bits define the handshake timing and the ATX7002 timing. The IO data is read or written in a parallel mode. The figures below show a possible timing in this mode. In AD converter testmode, Patternbit BHSO initiates the ATX signal DAC output change. A user pattern bit then starts the DUT-conversion. After the conversion time, pattern bits HB_OE_CLK and LB_OE_CLK clock (low to high transition) the DUT data into the input DIO input-register. BHSI then stores the captured data in the capture memory. In DA converter testmode, Patternbit BHSO initiates the data change on the DIO output. A user pattern bit then starts the DUT-conversion. After the conversion time, BHSI samples the DUT output voltage and stores the value in the DAC capture memory. To keep the DATA enabled, pattern bits HB_OE_CLK and LB_OE_CLK should be programmed high during the whole sequence

IM11: Byte-wise data transfer, Pattern bit generated timing

In this mode, the device data is divided in a least significant byte and a highest significant byte. In input mode (AD converter testing) , HB_OE_CLK clocks (low to high transition) the high significant byte, and LB_OE_CLK clocks (low to high transition) the low significant byte. The pattern bits generate both lines. The DUT data should be connected to the D0..D8. BHSI then stores the data in the capture memory. In output mode (D/A converter test), HB_OE_CLK enables the high byte output buffer and LB_OE_CLK enables the low byte output buffer. Therefore, both buffer outputs should be tied together.

IM20: Serial data transfer, Handshake mode timing

This mode is used for serial data transfer in handshake mode. The number of bits shifted in can be up to 24 bits. HSI1, HSI2 and HSO are used for timing and D0 as input. Handshake line HSO indicates that the DAC output voltage is valid and the DUT can start the conversion. (the output voltage of the DAC is supposed to be settled after the programmed settle time TS. The HSO active state is programmed with HM. HSI1 and HSI2 are handshake input lines, and the timing is therefore defined by the user. The converter data is then applied to DO, LSB first, and clocked by HSI1. HSI2 then indicates that the shifted data is ready and that the ATX controller can read the DUT DATA from the shift register. The active state of HSI2 should last for at least 2.5us. During that time there should be no more clocks on HSI1. The inactive state of HSI2 should be at least 4 us. The active state of Both HSI1 and HSI2 is programmed simultaneously. Note: if HSI2 did not become active within the defined timeout time(TO), the ATX samples the serial data latch, TO should therefore be defined, broadly TO prevents a timeout during serial data transfer.

IM21: Serial data transfer, Handshake mode timing

This I/O mode is the same as described for IM20. Now, the MSB is shifted in first and no extra clocks on HSI1 are allowed.

IM30: Serial data transfer, Pattern bit mode timing

The pattern bits define the timing of the serial data transfer and the ATX7002 timing. In the timing example below a possible timing is shown for a serial A/D converter. A user pattern bit is used to start the conversion, another pattern bit is used to clock the serial device, to get the serial data. In the DIO, An internal pattern bit called SERCLOCK is connected to the clock pin of the shift register. This clock bit should be programmed in conjunction with the user pattern bit, clocking the serial data from the DUT. When all bits are shifted in the shift register, the internal pattern bit BHSI captures (positive edge) and writes (negative edge) the shifted data in to the capture memory. The maximal number of bits that can be captured is 24 bit.

During A/D test, the edge of BHSO initiates the change of the stimulus data and set the shift register in parallel load mode. This data is then parallel loaded in the DIO shift register on the first edge of SERCLK. Immediately after this parallel load, BHSO should be set low, to set the shift register in shift mode during the parallel load, the first bit appears on the output of the shift register. The first data bit can then be clocked into the DUT, LSB first, using a user-pattern bit as serial clock. After clocking the DUT, SERCLK shifts the DIO shift register one step. This sequence is repeated until all data bits are shifted in the DUT. The DUT conversion then starts (possibly initiated by a second user pattern bit). The conversion result is then sampled and captured on BHSI. When shifting LSB first,Serclock should clock 24 times to align the data correctly into the 24 bit input shift register. If for example a 8 bit result is shifted in, there should be 16 extra clocks to align the 8 bits in the lower part of the shift register.

IM31: Serial data transfer, Pattern bit mode timing

This I/O mode is the same as described for IM30. Now, the MSB is shifted first.

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IO | Read or write digital IO port

With this command, the data value on the digital IO may be read or written. A write to the IO can be performed if the DIO is in parallel output mode and the IO mode is set to IM0 or 1. If the DIO is in output mode, and in IM0, the IO? command returns the previously written output data.

A direct read action from the DIO input pins can only be performed if the DIO is in input mode and in IM0 only. In other IM modes, the IO? reads from internal DIO data registers.

Related commands: IM, IOHS

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IOHS | Read/write handshake lines

With IOHS, the state of the handshake lines HSI/HSO may be read or HSO may be changed. When reading the status with IOHS? the first digit reflects the HSI1, state the second digit reflects HSO state. The HSI state reflected here is the state read directly from the DIO connector.

A state is reflected as "1" for active and "0" for inactive.

Depending of the HM command, "Active" can both be a logic "0" or a logic "1".

Normally HSI and HSO are controlled by the algorithm. The IOHS command is for debug purposes or for an automatic test of the loadboard connection.

Related commands: HM, IOHS

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M | measurement results

A/D and D/A linearity (ramp) test (MT1 and MT11):

• M0: Number of missing codes for A/D Ramp test
• M1: Offset error
• M2: Gain error
• M3: INLE, Integral linearity error (absolute value)
• M3+: positive INLE, Integral linearity error
• M3-: negative INLE, Integral linearity error
• M4: DNLE, Differential linearity error (absolute value)
• M4+: positive DNLE, Differential linearity error
• M4-: negative DNLE, Differential linearity error
• M5: TUE, Total unadjusted error (absolute value)
• M5+: positive TUE, Total unadjusted error
• M5-: negative TUE, Total unadjusted error

Errors are represented in LSBs. See command PMODE for End Point or Best Fit calculations.

More information about linearity parameter calculations can be found here.

A/D and D/A dynamic test (MT12 and MT12):

• M6: SINAD, Signal to Noise And Distortion
• M7: SNR, Signal to Noise
• M8: THD, Total harmonic distortion (7 harmonics)
• M9: Peak Harmonic
• M10: Spurious noise

Parameters are represented in dBs.

More information about the dynamic parameters can be found in the article Dynamic parameter calculations.

Related commands: PMODE, MT

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ML | Measurement loops

For MTs other than MT15:

During a measurement loop, of the stimulus data, stored in the signal DAC (A/D measurement) or in the DIO (A/D measurement) is output to the DUT. While the capture memory (in the DIO for A/D measurements, or in the ADC module for D/A measurements) stores the converter results. The number of stimuli steps within one loop is defined by the Stimulus Steps (SS) command. This loop can be repeated up to 255 times.

Note that the capture memory can capture 524288 conversion results. When the number of results recorded in the capture memory exceeds the memory size, the capture memory address counter stops, and the capturing of data will be terminated.

MT15:

During the test each code will be converted ML times before the next code is supplied to the D/A converter. If the total number of results do not fit in the ATX-ADC capture memory, the test will be divided in several cycles. The effective number of averages is: cycles *(av./cycle-outliers). See command OL.

Using the MFDIO in high speed mode the number of settle loop can be up to 4095.

Related commands: SL, MT, OL

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MLOCK | Lock/Unlock Module

An ATX7002 module can only generate a signal (DAC modules) or capture a signal (ADC modules) if the module is set in lock mode. If module is in lock mode the modules memory and configuration cannot be changed! So configure module before setting in lock mode. The MX (start test) will automatically set the module in lock mode and unlock the module after the test. Use this command only if you plan to use the module as (stand-alone) signal generator/digitizer.

Related commands: MMS, MMA

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MMA | Module Memory address counter

This command is implemented to read or write (edit) the module memory of the current selected module. MMA initiates the address counter, pointing to the memory location to be edited.

Related commands: MMD, MML, MMR, MMS, MMW

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MMD | Module Memory dump

This command dump a number defined by hex, of contents of the current selected module memory. The dump starts from the address defined by the MMA command. After command execution, this memory counter value has been incremented by the number of dumped memory contents.

Related commands: MMA, MML, MMR, MMW

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MML | Module data Load

This command stores a hex value to the module memory address. The destination address is pointed by the Address counter, initiated by the MMA command.

Related commands: MMA, MMD, MMR, MMW

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MMR | Module Memory single Read

This command reads the contents of one module memory address. The address should be a hexadecimal value.

Related commands: MMA, MMD, MML, MMW

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MMS | Module Memory end (stop) address

The stop address is the last address used during signal generation.

Related commands: MMA, MLOCK

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MMW | Module Memory single write

This command stores a hex value (m) to the module memory address at n.

Related commands: MMA, MMD, MML, MMR

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MT | Measurement Type

The following types of measurement are available:

• 1 A/D ramp test is set
• 2 A/D sine (dynamical) test
• 3 A/D user defined pattern generation
• 4 A/D Statistical and noise test
• 11 D/A ramp (linearity) test is set
• 12 D/A sine (harmonic) test is set
• 13 D/A user defined pattern generation
• 15 D/A ramp with only 1 ramp and many conversions (averages) per (DUT) converter step

All of these measurement types are started with the MX command. After the measurement is finished the ATX7002 sends a "P" to indicate that the measurement is ready.

Related commands: PMODE, MX, M

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MX | Execute measurement

When all parameters (Handshake- and IO-mode) are specified correctly, and the stimulus memory is filled with appropriate data, the measurement may be started. At the end of the measurement, the ATX7002 returns a "P" to indicate the end of the measurement.

Related commands: PMODE, MT, M

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OL | Outliers

Only for MT15 (D/A Ramp test with only 1 ramp and several steps for each converter step). For each outlier the maximum and minimum measured values per converter step (and per cycle) are removed.

Maximum averages per cycle is: capt mem./converter steps = 512k/16k = 32 times. So the total test takes 256/32 = 8 cycles. During 1 cycle each converter step is 32 times converted and 4 results are removed: 2 maximum values and 2 minimum values. So for this test the effective number of averages is 8 x (32-4) = 224.

Related commands: MT, ML

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OM[B]? | Output Measurement results

MT1 (A/D ramp test) and MT2 (A/D dynamic test) outputs the digital captured codes from the DIO module (hex). The number of elements is equal to SS. The settle conversions (SC) are not present in the output data.

MT4 (A/D Statistical test) output then number of code occurrences. The number of output elements is equal to 2^DB.

MT11 (D/A ramp test) and MT12 (D/A dynamic test) outputs the results from the ADC captured memory (adc hex codes). The number of elements is equal to SS.

MT15 (D/A ramp test with unlimited averages) outputs the results from the ADC captured memory (adc hex codes). The number of output elements is equal to SS.

The B (OMB) is optional. Data will be send in binary format. This command is used by the software ATView (version 7.1 or higher).

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PBA | Pattern bit generator start address

The PBA command defines the start address from which the pattern generator operates. This makes it possible to store more than just one pattern in the Pattern bit generator memory. Just choose a pattern by changing the start address. The start address is not only used during pattern generation, also during the pattern bit edit mode (The edit mode is entered with the PBE command), PBA defines from which address the edit starts.

Note: When PBA is defined, the return address defined by PBR is overwritten with the PBA address.

Related commands: PBR, PBE, PBC

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PBC | Pattern bit Clock

This command sets the clocksource for the patternbits, by setting a clocksource and a clock divider value. The DIO has one mounted crystal clock generator, clock1 and and optional crystal clock generator clock2. It is also possible select an external clock, connected to HSI2. With parameter n, the clocksource can be defined:

There is a diver between the selected clock and the pattern generator. This divides the clock frequency by a factor, set by m, ranging from 1 to 4096. The step time of the pattern bits can be calculated:

Related commands: PBR, PBE, PBA

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PBE | Pattern bit Edit mode

The patternbits can be edited while in editing mode, initiated by the PBE command. In editing mode, the ATX7002 has a separate command interpreter, for editing the pattern bits. The patternbit memory has a depth of 65535 steps and is 16 bits wide. The sequence of each bit in the pattern memory can be programmed separately. The bits are divided as follows:

The edit commands described below can be entered separated by a CR, LF or ";" (semicolon).

The edit position in the memory starts on the address defined by the PBA command. The edit position then shifts one step further than the last edited step. This way it is possible to enter various commands in a sequence, without overwriting the previously defined part of the pattern.

The Following edit commands are implemented in the patternbit editing mode:

Bn

Define the bit to be edited (n=0..15) example: B8 = Edit bit 8, start edit from PBA-address

CLn1,Hn2,Rn3

To define a repeated pattern within the complete pattern (n =decimal integer):

• where: n1 is the number of logic Low steps
• n2 is the number of logic High steps
• n3 is the number of times these steps (n1 and n2) are Repeated

or

CHn1,Ln2,Rn3

• where: n1 is the number of logic High steps
• n2 is the number of logic Low steps
• n3 is the number of times these steps (n1 and n2) are Repeated

Example: CH2,L3,R3 : the pattern generated is:

• Example:
• L3 pattern bit is 3 steps low
• H4 pattern bit is 4 steps high
• when these commands are entered after the command in the above example the pattern looks as follows:

Related commands: PBR, PBC, PBA

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PBR | Pattern bit generator return address

The return address defines the address, the pattern generator returns to after the first pattern run. The first pattern loop starts from the start address defined with PBA. This makes it possible to place a one-shot sequence in the pattern between PBA and PBR.

Related commands: PBA, PBE, PBR, PBC

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PMODE | Production mode

When PMODE is activated, the ATX7002 calculates error parameters after each test. These calculated parameters can be read with the command Mn. See the command description of Mn for further details. For ADC and DAC Ramp test select n=1 for the End Point error calculations or n=2 for the Best Fit error calculations. m is optional and determines the trip-point search algorithm for the ADC Ramp test. If m=0 (default value) the trip-point search method 1 is used. If m=1 the codes are sorted (method 2). See document AdcTrippointSearch.pdf for more information.

More information about linearity parameter calculations can be found here.

More information about the dynamic parameters can be found in the article Dynamic parameter calculations.

Related commands: MX, MT, M

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RA | Set Range

The WFD18 module has the following input ranges:

The WFD14-70 module has the following input ranges:

The AWG16-100 module has a proportional output ranging of 0.063V up to 5V. The output range can also be set in dBs: RAn,DB n can have a value between 0 and 18.

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S2D | Attenuation and wire mode

Set the attenuation and connection status of the Single ended to Differential mode path of the S2D+GA module.

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SC | Settle Conversions

A ramp consists of a step-by step increasing value. When a ramp is repeated, which is the case when the stimulus data is looped, because of more then one settle loop and/or one or more measurement loops, it will take a certain amount of time for the analog output stage to settle from the relative large output voltage change. With settle conversions, some additional steps are added to the start of the ramp. As a result, the ramp starts "ramping" after the output voltage has settled.

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SDI | Read Static Data Input Bits

The DIO has 4 static input data bits. The status of these bits can be read with this command.

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SDO | Write Static Data Output Bits

On the DIO, 8 static output data bits are available. The output bits are not changed or read during the measurement and can only be changed or read by means of this command. The static bits are meant for initial settings on the load board (i.e. relais etc), or for reading out a status from the loadboard. The bits may also be used for SPI or I2C emulation.

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SF | Fill Stimuli Memory

This command recalculates the stimulus data and fills the stimuli memory. After changing Stimulus definition parameters like MT, SS, SC, AN, AX, DN, DX, etc, the stimulus should be recalculated and stored in stimulus memory. Note that the module on which the stimulus memory is situated must be selected first with the C command. For a D/A measurement type, the stimulus memory is situated in the DIO. For a A/D measurement type, the stimulus memory is situated on a ATX7002 signal dac.

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SL | Settle loops

During a settle loop, the stimulus data is output to the DUT. While the capture memory does not store the converter results. The number of stimuli steps within one loop is defined by the Stimulus Steps (SS) command. A maximum of 255 settle loops can be programmed, to let filters on the testboard settle. The loops can only be stopped by sending an ESC-C. This setting should only be used for debugging the test setup.

Using the MFDIO in high speed mode the number of settle loop can be up to 4095.

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SS | Stimuli steps

This command sets the number of Stimuli Steps. For defining an analog ramp the following formula should be used to calculate the number of stimulus steps needed:

For a digital ramp, the number of stimuli steps can be calculated as follows: SS = Startvalue - Stopvalue +1.

When defining a sine wave, it is best to choose a prime number of stimulus steps. The number of stimulus steps, the number of sine-periods within one stimulus loop and the cycle determine the Sine frequency:

After defining a new number of stimulus steps, the stimulus memory should be updated with the command SF.

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SW | number of Sweeps

Because the capture memory size is limited, the number of times a ramp is applied to the device under test (set by the command Measurement loops, ML) and captured by the capture memory would be limited. To prevent these problems for the statistical tests, the Sweeps command overrules the measurement loops command. It calculates the contents of the stimulus memory, using the ramp-setting commands and puts one, or even more ramps in the stimulus memory. The number of measurment loops is calculated so, that the number of data fits in the capturememory. When running the measurement, the measurment loops are repeated until the defined number of sweeps is applied to the device under test. Everytime the memory loops are repeated, an intermediate statistic calculation is done on the captured data.

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TC | Cycle time

This command specifies the effective sample time. It should be entered separately because the sample time is depending of lots of parameters, like the frequency of the pattern-bit clock, which can be a clock applied by the user, the frequency of a user applied sample clock, the length of the pattern data block etc.

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TO | timeout

The timeout time is a parameter that is used when the ATX7002 is used in handshake mode (IM 0..3, 20..21). It defines the maximal waiting time that the ATX7002 waits for HSI. For more detailed information on handshaking please refer to the command description of IM and HM. The time can be set from 0us to 2000000us (2 sec.)

Related commands: TS, HM, IM

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TRG | trigger mode

For the 24 bit and 18 ADC the trigger source can be selected with the second parameter:

24 bit ADC

18 bit ADC

14 bit ADC

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TS | timeout

The settling time is a parameter that is used when the ATX7002 is used in handshake mode (IM 0..3,20..21). It defines the time between a DAC output voltage update or dio output code change and the activation of HSO.

Related commands: TO, HM, IM

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TST | Perform selftest

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WAIT | Wait

This command waits n microseconds before proceeding to the next command. It may be used for additional -user board- settling time after switching on a power dac, or to pause after other events that require a settling time.

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ESC-C | Abort current action

This command may be issued at any time and returns the ATX7002 to the command mode. The settings are not changed. ESC-C stands for ASCII code 27 (decimal or 1B hex) and code 99 (decimal or 63 hex or character c).

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